Global Memory Fab Expansion & Equipment Demand (2026-2028)

— From Maker Capex to the Tool-Level Transmission Map

About this piece: A structured read of the 2026-2028 memory build-out and the equipment it pulls, refreshed with this week's Korean investment-week deltas (verified 2026.6.26-7.3). Structure: makers → equipment overview → tool-by-tool → investment framework. Companion interactive map: memory-fab-map-en.pages.dev. Figures marked "model/est." are modeled, not official disclosure; two hard data conflicts are flagged "unverified" (see Appendix B).

How to read this

Three paths:

• 10 minutes: read the "one-page conclusion" + look at the 13 figures (each chapter's figure is its conclusion).
• 30 minutes: read each chapter's opening qualitative paragraph and reader-view table; skip the collapsible detail.
• Deep read / review: use the collapsible tables and Appendix B (data-conflict log) to reconcile.

Confidence tags (one scheme, used throughout):

On the equipment side, the analytical tiers map roughly as: proof-the-slope ≈ has official/reported revenue or order evidence; option-to-proof ≈ direction confirmed but no customer-share evidence; theme ≈ mechanism holds but no order evidence.

Four hard rules (every number passes these four gates):

1. Backend packaging/test capacity is not added to front-end WPM (Cheonan/Onyang, P&T7, Indiana, Singapore AP carry no WPM);
2. NAND→DRAM conversion is not counted as net-new cleanroom;
3. Policy/roadshow ten-year headline numbers (2,655T, 896T, 600T) are not converted into 2026-28 WFE;
4. Cleanroom area and satellite images are not reverse-engineered into WPM.

One-page conclusion

1. This is not an ordinary memory cycle. AI demand is repricing four bottlenecks at once: advanced DRAM/HBM front-end wafers, HBM backend conversion (sellable HBM), NAND's role in AI-inference storage, and national-scale fab infrastructure. A single dollar of capex flows in sequence through construction → cleanroom → tool move-in → qualification → supply, and each stage benefits a completely different set of suppliers.

2. The 2026 supply paradox is where the whole story starts. Headline capex is unprecedented (Korea alone announced ₩3,200T-scale roadshow numbers in a single week), yet 2026 global DRAM net add is only ~110-120k wpm — Samsung revised down to just ~15k (P4 ramp pushed to Q4, conversion not counted as net add, old lines exiting) [est.]. Layered onto HBM's 3-4× wafer consumption, commodity DRAM supply grows almost zero. The price surge (1Q26 contract +90-95%) and the equipment orders are two sides of one coin: supply can't be released, so the money keeps flowing into the chain that "makes expansion land."

3. The right read of this week's (6.26-7.3) Korean "national investment roadshow week": the big numbers (Samsung's 10-year 2,655T, Honam 896T MOU, SK 1,100T) are political pricing and don't enter the 2026-28 model; the real deltas are four: ① SK split Cheongju 100T for the first time into an 80T NAND fab M17 (ops 2027, output 2029H1) + 20T packaging — the first big anchor for a Korean NAND-WFE restart; ② Samsung's 56T into Cheonan/Onyang, with Onyang adding 5 HBM backend lines — an escalation of the HBM packaging arms race; ③ SK's ADR prospectus disclosed 11.9T of EUV purchases (through 2030) — a rare company-level EUV figure disclosed directly; ④ Yongin Fab1's first cleanroom pulled forward to 2027.2 — SK's front-end WFE order window a quarter earlier.

4. Rank equipment by "timing × bottleneck × evidence," not by total capex. In 2026-27, watch facilities/gases/cleanroom, HBM backend (bonding/test/inspection), and process control first; in 2027-28, watch front-end WFE moving in en masse (Yongin 2027.2 cleanroom, P4/P5, M17) and the NAND generation switch; only after 2028 do you calibrate the long-dated options (P5 full ramp, Yongin full config, Clay NY, CXMT Fab4).

5. The landscape in three lines: near-monopoly segments (ASML/KLA/DISCO/TEL Track/Lam HARC) deepen their moats in the AI era with a rising certainty premium; the platform player (AMAT) is structurally eroded by "narrow-and-deep" specialists (FY25 +4% vs WFE +15%); the HBM new categories (TCB→hybrid bonding) have the most elasticity but the least-settled landscape — the process-generation switch is the window where customer lock-in reshuffles. Domestic substitution scales at mature nodes (etch/deposition >40%, thermal >60%), while lithography (~18%) and metrology (~25%) are the hard ceiling.

6. The single most important discipline: capex ≠ WFE orders ≠ bit supply. Any project that sits two consecutive quarters at "construction / policy headline" with no cleanroom delivery, tool move-in, or customer-qualification evidence should be downgraded from near-term equipment beta to a long-dated option.

Chapter 1 — Makers: read the people, then the money, then the timing

1.0 This week's delta: Korea's "national investment roadshow week" (6.29-7.2) ★

This week was a watershed for reading the Korean build-out: 6/29 Blue House briefing (two chairmen's speeches + same-day disclosures) → 6/30 Gwangju MOU + Samsung's 10-year plan → 7/2 Chungcheong-region announcement. Three events formally elevated Korean memory expansion from "corporate action" to "national project." But for equipment research you must separate political pricing from trackable deltas.

Full list of this week's new numbers (verified 2026.7.3)

Core numbers unchanged this week (to prevent misreading as new): Samsung 2026 capex+R&D >110T (disclosed 3/19, group-level); P4 mass ramp in 2026Q4; HBM4 in mass production since 2026.2 and sold out for the year; SK M15X wafers in since 2026.2; Indiana and HBM4/4E customer shares saw no new numbers.

The call: where political pricing ends and real deltas begin

The 6.29-week ₩3,200T-scale aggregate (implied real semi increment estimated ~₩1,300-1,700T) is a cross-period, cross-division combined figure; its signal value is in directional discipline (speeches + same-day formal disclosure, lowering the "just talk" risk), not the dollar amount. Ranked by verifiability, the items that actually move 2026-28 equipment demand:

1. M17 (80T NAND) — positive for the deposition/HARC-etch chain (Lam/TEL/AMAT); 2027 groundbreak means tool move-in from 2028;
2. Onyang 5 HBM lines + 56T — more direct buyers of TCB/hybrid bonding, thinning, probe cards, ATE, inspection;
3. SK 11.9T EUV purchase — company-level evidence supporting ASML's memory order slope;
4. Yongin Fab1 cleanroom 2027.2 — cleanroom completion = tool move-in; 2027 becomes SK's big front-end WFE order year;
5. Honam/Southwest ten-year framings — for now, facilities far-dated pipeline only.

1.1 The geography: read the world in three tiers

Read the global map in three tiers by when supply lands: near-term supply (2026-27 equipment orders: Pyeongtaek P4, Cheongju M15X, Kitakami K2, Tongluo P5, Singapore HBM AP, Hefei/Wuhan); mid-term supply (2027-28 tool move-in: Pyeongtaek P5, Boise, P&T7, Indiana, Fab 10B, M17); long-dated options (2028+, facilities first: the two Yongin clusters, Clay NY, Honam/Southwest hub, CXMT Fab4). The more far-dated the project, the more the current beneficiary skews to construction/power/gas/cleanroom.

The key geographic fact for Korea: within 100 km south of Seoul sits the single largest memory expansion in the world. Pyeongtaek (Samsung P1-P5) and Cheongju (SK M15/M15X/P&T7/M17) are the 2026-28 near-term battleground; the two Yongin clusters (Samsung 360T + SK 600T framing) are the "second Pyeongtaek," pulling facilities first from 2027; Cheonan/Onyang (Samsung) and Cheongju P&T (SK) carry the HBM backend; the Gwangju/Jeonnam Southwest hub is a 2030+ policy option.

1.2 Samsung: catch-up + conversion + backend relief

One-line read: Samsung's problem isn't money — it's connecting Pyeongtaek's wafers, conversion's product mix, and Cheonan/Onyang's backend in the same time window — largest capex ≠ fastest sellable HBM.

Equipment read: Samsung's money splits into three chains — Pyeongtaek front-end WFE (litho/etch/deposition/CMP/metrology across the board); conversion retooling (the focus is process control, not whole new lines); Cheonan/Onyang backend (bonding/thinning/probe/ATE/inspection, mostly in-house via SEMES but the outsourcing ratio is the key track). The chairman this week defined the HBM plant as a "main-fab-grade" process flow — the first time management elevated packaging to front-end-grade capex intensity, direct evidence for re-rating backend equipment intensity.

Falsifiers: P4/P5 tool move-in slower than the model → front-end slope cut; 1c yield (currently ~70%, pushing 80%) or HBM4 customer qualification short → front-end expansion can't turn into sellable HBM; Cheonan/Onyang tools and qualification out of sync → catch-up stays capped by the backend.

1.3 SK hynix: integrated HBM system expansion

One-line read: SK is not a single-point expansion — it strings M15X (near-term front-end) → Yongin (long-term greenfield) → P&T7/Indiana (backend) → M17 (NAND restart) into a complete HBM/storage system chain — the most complete evidence chain of the five.

Equipment read: M15X is the most front-end-heavy (ASML/TEL/Lam/AMAT/KLA/SCREEN); Yongin in 2026-27 is EPC/power/gas/UPW/AMHS (SK ecoplant as GC), entering the WFE window after the 2027.2 cleanroom delivery — the 11.9T EUV purchase plan in the ADR prospectus (to 2030) effectively "pre-announces" the lithography leg of this chain; P&T7/Indiana pull Hanmi/ASMPT/DISCO/Advantest/FormFactor/Onto/Camtek; M17 is the new NAND deposition/HARC-etch order pool from 2028.

Falsifiers: M15X ramp or HBM4 qualification slow → near-term add cut; Yongin cleanroom cadence (one per 6 months) missed → pre-2030 slope cut and the facilities→WFE lag lengthens; P&T7/Indiana qualification delayed → front-end die stuck at sellable conversion; if M17 slows on a NAND price fall → the NAND-WFE restart is falsified.

1.4 Micron: milestone-based capex story

One-line read: Micron deliberately discloses no fab-level WPM — the right read is to track milestones (first wafer / meaningful shipments / AP capacity) and the shape of the money (construction vs equipment, customer prepayments).

• Capex: FY2026 ~$27B (FQ4 ~$10B); FY2027 each quarter above FQ4-26, over half the YoY increase from construction (construction-type +$10B+ YoY) — the most direct evidence of construction-first [official].
• Strategic customer agreements: ~$22B committed (~$18B cash deposits), 16 agreements, take-or-pay + price floor/ceiling, covering ~20% DRAM and 1/3 of NAND volume — turning commodity into a platform contract, an institutional difference vs the Korean makers [official].
• Policy: up to $6.4B in grants + a 35% investment tax credit [official].

Falsifiers: prepayments can't convert to tool install / customers renegotiate → the capex demand anchor weakens; any critical path of Tongluo/ID1/Singapore AP delayed → 2027-28 supply timing slips; backend bottleneck (stacking/test/probe/substrate) exceeds front-end improvement → HBM revenue converts slower than capex.

1.5 SanDisk/Kioxia: physical network + JV economics

One-line read: SanDisk and Kioxia are not two separate capacities — Yokkaichi/Kitakami are the physical anchor, the JV is the economic allocation mechanism (the JV covers ~80% of Kioxia's manufacturing, each takes ~50% of output, SanDisk bears 49.9-50% of capital obligations). Summing the two double-counts.

• JV extended to 2034.12.31 (was end-2029); SanDisk pays $1.165B (2026-2029) — removing the mid-term cliff, the framework covers Gen10/Gen11 and the AI-inference cycle [official].
• Kitakami K2: in production 2025.9, ramps 2026H1; its core purpose is cleanroom space for migrating existing capacity to newer nodes — not a greenfield-WPM story [official]. BiCS10 (332 layers) mass production 2026H2; Kioxia argues 332 layers + lateral scaling + CBA beats a 400+ layer path (company view, not third-party verified).
• Capex: Kioxia ~JPY 470B/yr over three years (explicitly includes cleanroom interiors and infrastructure, not pure equipment) + R&D ~JPY 230B/yr [official].
• Demand side: NAND "sold out" in 2026; SanDisk FQ3'26 revenue $5.95B (+97% QoQ), datacenter revenue +233% QoQ — note the caveat: the 78.4% GM may be over-annualized by the market [official / unverified].

Equipment read: NAND's equipment elasticity is not in lithography but in deposition (+50% steps by layers), HARC etch, clean/CMP, metrology, CBA bonding; K2/BiCS10 are "cleanroom reuse + straight to tools" conversion demand — the fastest cadence. Falsifiers: NAND ASP falls fast in 2026H2 → 470B capex reads as aggressive supply and the SanDisk elasticity is falsified; Gen10/CBA qualification slow → the technology premium compresses.

1.6 CXMT/YMTC: domestic supply response + domestic-tool proving window

One-line read: CXMT is a counter-variable on the commodity-DRAM supply curve and a proving window for domestic tools — not a near-term global HBM fix; YMTC is the same for NAND.

• CXMT: ~350k wpm today (near Micron's 385k), 2028 target ~500k (~17% global), 2030 model 600k — all modeled (est.); officially only the existence and product direction of three fabs is confirmed; Fab3 ramping (150→200k), Fab4 an option. $4.2B IPO approved; HBM3 mass-production target end-2026 (yield ~25%, in R&D); DDR5 cost +30% vs the big three; sub-1b constrained by tool export controls. 2026 equipment tenders ~RMB 35-43B (channel est.).
• YMTC: Wuhan Phase III pulled forward (target ops end-2026) + two new fabs planned; Xtacking 4.0 ~270 layers; domestic-tool share >50%, core-step localization >60% — the largest proving platform for the domestic chain; ~half of Phase III capacity pivoting to low-power DRAM to prep for HBM (est.).

Equipment read: the main order pool for domestic tools (NAURA/AMEC/Piotech/Hwatsing/ACM); the control exposure for overseas tools (Lam China revenue ~35%, KLA China -9%). Falsifiers: any of DDR5 server qualification, yield, or HBM backend capability short → supply response cut; controls escalate (the MATCH act already bars immersion DUV and cryo etch to China) → expansion forced to slow.

1.7 Summary: timeline and capacity bridge

Evidence-strength contrast across the five (the easiest mistake in integration is putting all five in one precision table):

Global figures (est.): global DRAM ~2,050k wpm today, 2026 net add only ~110-120k; Samsung+SK+CXMT 2026E 1,650k → 2030E 2,540k (+890k). Global NAND ~890-930k, Korean makers shrinking (Samsung -160k over 5 yrs), Japanese makers scaling layers, YMTC expanding — NAND is this cycle's strategic sacrifice, positive for ASP mid-term; M17/Fab 10B are the new WFE only from 2027.

Chapter 2 — Equipment overview: from capex to tools

2.1 Core framework: one dollar, four destinations, 18-30 months apart

This is the single most important figure in the report. The four-step check chain for any "XX-trillion investment" headline: spend type (which chain) → equipment chain (pulls whom) → proof source (any order/move-in evidence) → falsifier (when to void the call).

Four transmission principles:

1. Judge project type first, then the tool. For greenfield (Yongin/P5/Clay NY) the first beneficiary is not ASML but EPC/gas/power/UPW — facilities lead WFE by 18-30 months. Yongin's real-world evidence (147,000 m² cleanroom, 2,312m utility tunnel, 345kV power) is this chain happening now.
2. Conversion/brownfield is fastest. P2 conversion, Tongluo P5, K2/BiCS10 skip construction and go straight to tools — the main 2026-27 equipment elasticity.
3. The real HBM bottleneck is usually backend. All three packaging fabs (Cheonan 2027.12, P&T7 end-2027, Indiana 2028H2) come online after end-2027 → the HBM supply-demand gap lasts at least to 2028, and the backend order window is exactly 2026-2028.
4. NAND equipment beta doesn't follow DRAM's EUV logic. NAND uses no EUV today; the elasticity is in deposition/HARC etch/clean/metrology.

2.2 Five equipment demand-pull lines

Demand increment = WPM increment × per-wafer tool-process intensity × yield adjustment. Multiplier effect: a project that triggers several lines at once (M15X = DRAM front-end + HBM front-end + HBM backend feedstock) can reach 3-5× the equipment demand of a single-line project; every 10k HBM wpm pulls the front-end ≈ 40k standard-DRAM wpm.

2.3 Market totals: the anchor and structural divergence

Three structural reads: ① backend (+48%) > NAND (+45%) > packaging (+20%) > DRAM (+15%) > WFE average (+11%) — the growth gap is the market's validation of the "five pull lines"; ② in a memory line, equipment is 70-80% of total investment, of which etch + deposition is roughly half (est., for rough sizing); ③ in 2026 AI (HBM/GDDR7) consumes nearly 20% of global DRAM-equivalent wafer capacity — front-end intensity and the backend bottleneck rise together.

2.4 Equipment-segment navigation table

Note: shares are approximate and most cannot be supported to single-digit precision by primary sources; kept for framework use, to be sourced case-by-case in single-name work.

2.5 Three-tier beta and the allocation summary

• Proof-the-slope (certainty cross-checkable with totals + company financials): ASML, TEL, Lam, AMAT, KLA, Advantest, Teradyne, FormFactor, Onto.
• Option-to-proof (direction confirmed, customer share to be proven): BESI, ASMPT, Hanmi, SEMES, DISCO, ACCRETECH, Technoprobe, Ebara, Kokusai, SCREEN, Nova.
• Time-lag tracking (facilities): Linde, Air Liquide, SK ecoplant, Samsung C&T have project proof; Exyte / Samsung E&A are capability proof.
• Thematic (domestic): ACM, NAURA, AMEC have company-level revenue/product evidence; the localization rate itself is not proof.

Three things not to write: don't write "memory capex = ASML/Lam/AMAT all benefit"; don't write HBM bonding/ATE/probe elasticity as unlimited certainty; don't write domestic substitution as global leading-edge substitution.

Chapter 3 — Tool by tool: the deep dive

Each section uses one template: what it is (physical intuition) → landscape & moat → how this cycle pulls it → tracking signals. Start the five front-end sections with this overview:

3.1 Lithography + Track: monopoly pricing power, structural memory upside

What it is: projecting the circuit pattern onto the resist (litho) plus the coat/develop that pairs with it (Track). Advanced DRAM needs 60-80 lithography layers — the most litho-intensive track in memory.

Landscape: ASML monopolizes EUV (100%), ~85% of all litho; the moat is source (Cymer) + Zeiss optics + ecosystem, a triple composite with a 12+ yr catch-up. TEL holds Track ~90% (EUV Track 100%), 30 years co-developed with ASML; the biggest far threat is Lam's dry resist (early stage).

How this cycle pulls it: ① DRAM node migration is the core — 1c EUV layers rise to 5-7 (Samsung trimmed from 8-9 for yield; SK at least 5-6), 4F²/VG architecture keeps lifting intensity; ② an ADR prospectus disclosed 11.9T KRW of EUV purchases (to 2030) — a rare company-level figure disclosed directly; ③ Micron on a multi-year ASML EUV supply deal (1-gamma ramping, 1-delta 2027H2); ④ NAND uses no EUV today (only possible above 400 layers), don't count NAND capex into ASML.

Tracking signals: ASML memory-order share; EUV tool allocation across P4/M15X/Yongin; High-NA validation progress in DRAM (post 2027-28).

3.2 Etch: HARC is the highest-value segment this cycle

What it is: carving material away by the litho pattern. NAND channel holes (HARC) must drill ~50:1 aspect-ratio holes through 200-332 stacked layers (heading toward 100:1) — like drilling a 1-meter-wide straight well down from the 10th floor.

Landscape: Lam leads NAND deep-silicon etch (cryo, -100°C, adopted in HVM by all leading makers, supports 400+ layers); TEL monopolizes DRAM capacitor etch and attacks NAND with -70°C cryo dielectric etch; AMAT is strong in conductor etch (+3pp to #1). TSV deep-silicon etch (DRIE): Lam is currently exclusive to the top makers, with AMAT/AMEC in validation — HBM volume makes TSV etch Lam's second growth curve.

How this cycle pulls it: NAND layers 218→332 make HARC steps grow super-linearly (ARDE); the DRAM 4F² transition adds high-aspect-ratio etch; TSV adds 15+ new sub-steps. The 2025 NAND-tool +45.4% is mostly etch + deposition.

Tracking signals: Lam NVM revenue (FY25 +2.5×); order cadence at K2/BiCS10, M17, Fab 10B; TEL cryo-etch share progress in NAND; AMEC 85:1 (already into a NAND maker's 232 layers) → 90:1 validation.

3.3 Deposition: biggest NAND-layer beneficiary + a material-transition increment

What it is: "plating" conductor/insulator films layer by layer (CVD/ALD/PVD). Every 3D-NAND layer needs deposition — 200→300+ layers means +50% deposition steps.

Landscape: AMAT overall leader (PVD >50% is the fortress); ASMI is the ALD specialist (single-wafer ALD mid-50s%, 9 straight years of double-digit growth); Lam/TEL split by film type; Kokusai/Wonik in furnaces. The W→Mo metallization transition is the new variable: Lam's first production-grade Mo ALD (2025.2), with AMAT slow to respond — the material-generation switch is reshaping deposition share.

How this cycle pulls it: NAND layers (biggest driver) + DRAM HKMG adoption + HBM front-end ALD intensity; the 2026-27 K2/BiCS10 conversion, M17, Fab 10B, and YMTC Phase III are all deposition order pools.

Tracking signals: ASMI memory-order share; Mo-ALD adoption at the big three NAND makers; Piotech (PECVD +75%) ramp on domestic lines.

3.4 CMP + Clean + Thermal: the invisible intensity amplifiers

What it is: the "planarize" (CMP), "wash" (clean), and "anneal" (thermal) between every cycle. Step count scales linearly with process complexity; HBM's TSV reveal is the hardest CMP step (TTV<5%, two-stage process).

Landscape: CMP: AMAT ~65% (Reflexion), Ebara ~25% (strong in memory oxide CMP) — 18-24 month qualification lock, hard to pry short-term; ASMI entered via Axus. Clean: SCREEN/TEL lead; ACM differentiates with megasonic (~8% global). Thermal: relatively low barrier, highest domestic localization (>60%, NAURA lead).

How this cycle pulls it: HBM hybrid bonding imposes new CMP requirements (Ra<0.5nm, copper dishing 2-5nm) — a 2027-28 increment; the advanced-DRAM yield war lifts clean/particle-control value.

Tracking signals: Ebara memory-CMP orders; Hwatsing (local CMP >90%, 1000th tool shipped) share at CXMT/YMTC; hybrid-bond-surface CMP tool selection.

3.5 Metrology / Inspection: the AI-era "yield-tax collector"

What it is: every cycle gets a "health check" — defect inspection, CD metrology, overlay. Memory has 40%+ more inspection steps than logic.

Landscape: KLA ~63%, moat is a flywheel of 15,000 installed tools × 30 years of defect data — "hardware copyable, data not" — the only WFE segment with no strong substitute. Onto is this cycle's clearest share-migration story: Dragonfly G5 (150nm defects, 5× throughput) won double-digit orders from a top HBM maker + a $240M multi-year agreement (to 2027) — forming a "dual supplier" setup vs KLA in HBM inspection, though the erosion is limited to HBM.

How this cycle pulls it: HBM's 4× wafer multiplier → inspection demand magnifies; TSV/microbumps introduce new defect types; high-aspect-ratio structures (NAND hole bottoms) spawn e-beam/acoustic metrology demand. This is the best mix of "certainty × elasticity."

Tracking signals: KLA memory-revenue share (~34%); Onto follow-on orders (whether it extends to a second HBM customer); domestic metrology validation (~25%, the weak point).

3.6 HBM mid-stream: TSV, temporary bonding, thinning & dicing

What it is: the difference between HBM and ordinary DRAM is "through-hole (TSV) — thin — stack." Dies must be thinned to 30-50μm (HBM4 era <30μm, 1/20 of a credit card's thickness), then 12-16 stacked.

Landscape & pull:

• TSV drilling: Lam DRIE (see 3.2); electroplate fill + anneal; TSV reveal CMP (see 3.4). HBM4's I/O doubles to 2048-bit → TSV count doubles, intensity up another notch.
• Temporary bond/debond: EVG (IR LayerRelease) + SUSS (XBS300) duopoly — thin wafers must be carrier-bonded to process, an invisible beneficiary of HBM volume.
• Thinning/dicing: DISCO >70% monopoly, TAIKO process (keeps a 3mm edge ring) + tool/consumable/process-service triple-lock, ~70% gross margin; 1Q25 shipments ¥93B a record. 12-layer HBM thinning is 1.5× the 8-layer; hybrid bonding demands TTV<1μm, magnifying DISCO's edge. ACCRETECH is the second supplier.

Tracking signals: DISCO shipments and lead time; EVG/SUSS orders; the mid-stream tool lists for Onyang's 5 new lines and P&T7.

3.7 Bonding (TCB → Hybrid): the most elastic, least-settled segment

What it is: bonding 12-16 dies layer by layer with heat and pressure (TCB); in the HBM5 era it shifts to direct copper-copper (hybrid bonding, no microbumps). The tightest HBM backend bottleneck today.

Landscape (four-way fight + in-house):

TCB market ~3× in 3 yrs ($0.46-0.76B → 2027 ~$1.5-1.6B, two ranges in App. B). Hybrid switches 2027-28 (HBM4 still uses microbumps, JEDEC thickness relaxed to 775μm to leave room for 16 layers; HBM5 fully switches): BESI+AMAT vs ASMPT standalone vs Hanmi+TES catching up — tool lead time 12-18 months, 2026-28 capacity already locked by orders.

Investment read: the process-generation switch = a customer-lock reshuffle. Hanmi's TCB share does not auto-migrate to hybrid; conversely, whoever wins the first HBM5 hybrid orders locks in 2028-30. Tracking signals: who wins the 2026.3 ~100-tool TCB order; Onyang's 5-line bonding selection (SEMES vs outsourced); BESI's hybrid orders from memory customers; MR-MUF vs NCF vs hybrid roadmap declarations.

3.8 The test chain: probe card, ATE, inspection — the invisible ceiling on "sellable HBM"

What it is: a 16-layer stack = 16 KGD tests per unit + 1 post-stack test; HBM4 single-die test time is +30-50% vs HBM3E; final test of an accelerator with 8 HBM stacks stretches from ~50s to 20+ min. If test can't keep up, nameplate capacity never becomes sellable supply.

Landscape:

• Probe card: FormFactor leader (DRAM probe card +70% YoY in Q1'26, one HBM maker is 29.5% of its revenue), moat is the interface standard across 10,000+ probers; Technoprobe/MJC chasing. Probe cards are custom to the TSV layout with long lead times — the "invisible consumable tax" of HBM expansion.
• ATE: Advantest (memory-test leader, T5593; FY25 revenue +44.7%, OPM 44.2%; capacity 7,500→10,000 units/yr) + Teradyne (Magnum 7H aimed at HBM) duopoly ~90%, software lock (millions of lines of test code, 6-18 month switch) keeps it extremely stable.
• Package inspection: Onto (see 3.5) + Camtek.

How this cycle pulls it: backend test tools +48.1% in 2025 is the fastest of any segment — a direct map of HBM complexity, and the debate is whether it's a "short-term mismatch" or a "structural new normal" (each generation lengthens test time → per-unit test volume outgrows capacity expansion). We lean to the latter, using Advantest utilization as the falsifier.

Tracking signals: Advantest memory-tester revenue guidance (CY26 $2.2-2.7B); FormFactor Korea revenue; tester buys at P&T7 (WT line 2027.10) and Cheonan.

3.9 Facilities: time-lag arbitrage, reinforced this week

What it is: EPC, bulk/specialty gases, ultrapure water (UPW), power, AMHS (overhead transport), cleanroom — the first revenue wave of any greenfield, booked 6-12 months after groundbreak, leading WFE by 18-30 months.

Landscape: EPC market ~$47.2B (Exyte #1 at 10.3%; customer lock: Samsung C&T↔Samsung, SK ecoplant↔SK (Yongin GC), Bechtel↔N. America); gas duopoly Linde (project proof at a Korean fab) / Air Liquide (project proof at SK P&T7 and Micron Idaho); UPW Japanese top-3 (Kurita/Organo/Nomura) >80%; power ABB/Schneider; AMHS Daifuku/Murata.

How this cycle pulls it: this week stretched the far pipeline again — the Honam cluster needs 6.3GW power, 650k tons water/day (government promises up to 100% fiscal support); Yongin Fab1's 154kV backup + 345kV power and 2,312m tunnel are happening now; Micron FY27 construction capex is +$10B+ YoY. Note the non-standard disclosure and few pure-play names — more of a leading indicator than a direct holding pool.

Tracking signals: SK ecoplant Yongin progress (one cleanroom per 6 months); Exyte semiconductor order book; gas-company long-term-agreement announcements.

3.10 Domestic substitution: fast copy-and-scale at mature nodes, a fight at leading nodes

Two readings first: an adoption reading puts 2025 new-capacity localization at 35% (marginal speed); a penetration reading puts installed at 23.2% (2030E 39%). Both hold — incremental fast, installed low, overall still early.

Drivers & constraints: policy requires new lines >50% domestic; the MATCH act (2026.4) bars immersion DUV + cryo etch to China — "sanction→forced substitution" is clearest in etch/deposition, but the litho/metrology ceiling means a domestic line can't build a standalone leading-edge process line. CXMT 2026 tenders (~RMB 35-43B, est.) and YMTC Phase III (>50% domestic) are the main order pools; NAURA (RMB 39.4B revenue, +30.9%, booked into 2027Q1) is the platform representative.

Tracking signals: CXMT tender win structure from Q2; YMTC core-step localization rate; control-list changes; validation progress of the domestic HBM chain (hybrid bonding etc).

Chapter 4 — Investment framework & tracking system

4.1 Allocation tiers (by evidence grade, not story size)

Note: this is a proof-tier ordering, not an expected-return ordering — the most certain segments are usually the most fully priced; excess return more likely appears at the moment "option-to-proof upgrades to proof" (e.g., Onto winning HBM orders, ASMPT confirmed as SK's #2).

4.2 Five milestone gates and the 2026-2028 tracking calendar

Five gates: construction → cleanroom readiness → tool move-in → first/pilot wafer → customer qualification. Which gate a project sits at decides which tools it pulls right now.

4.3 Falsifiers: a three-tier refutation system

• Tier 1 timing slip (valuation-cadence issue): milestone slips but direction holds — P4 ramp, Yongin cleanroom, Tongluo retrofit slip a quarter or two. Response: adjust cadence, not conclusion.
• Tier 2 conversion failure (changes the equipment-chain structure): front-end wafers can't become sellable HBM/SSD — 1c/HBM4 yield short, customer qualification fails, backend can't keep up, prepayments don't convert to tool install. Response: re-weight equipment segments (the backend-bottleneck thesis strengthens or is falsified).
• Tier 3 thesis break (rewrite the main line): demand/price/policy-level change — HBM sold-out window shortens, the 1Q26 +90-95% price surge stalls and rolls over (top signal), AI-accelerator shipments slow, controls escalate sharply, NAND ASP falls fast in 2026H2 (470B capex reads as aggressive supply). Response: full re-rating.

Downgrade rule: any project that sits two consecutive quarters at construction/policy headlines with no cleanroom delivery / tool delivery / qualification signal → downgrade from near-term equipment beta to a long-dated option (closest to triggering now: Gwangju/Honam, CXMT Fab4, Southwest 400T).

4.4 Quarterly review template (seven evidence types)

Score seven evidence types each quarter to drive proof-tier up/downgrades: ① cleanroom opening (Yongin cadence is the gold sample); ② tool move-in (P4/M15X/Tongluo); ③ pilot/first wafer (ID1, Yongin 2027H2); ④ customer qualification (HBM4/4E, BiCS10, CXMT DDR5); ⑤ backend capacity (TCB tool count, tester count, packaging-fab completion); ⑥ capex split (construction vs equipment, Micron's quarterly disclosure is the best anchor); ⑦ confidence drift (whether modeled numbers diverge more from what lands officially).

Appendix

Appendix A — Definitions & glossary

• WPM: 300mm wafer starts per month (thousands/month = kWPM). HBM front-end WPM is a product allocation within DRAM wafers — not additive; backend packaging/test projects carry no WPM.
• Four "don'ts": don't add backend WPM / don't count conversion as net add / don't convert policy framings into WFE / don't reverse-engineer capacity from area or satellite images.
• Milestone dictionary: first wafer ≠ volume (several quarters apart); meaningful shipments/output = a customer-visible volume; mass ramp = the main ramp.
• HBM lineage: HBM3E (12 layers, microbump+TCB) → HBM4 (mass production 2026, 16 layers, still microbump, I/O 2048-bit → TSV doubles) → HBM4E (samples 2026) → HBM5 (2027-28, 20+ layers, hybrid bonding).
• NAND generations: BiCS8 218L (CBA) → BiCS10 332L (2026H2); Samsung V9 286L; SK 321L; YMTC Xtacking 4.0 ~270L.

Appendix B — Data-conflict log (check before citing)

Appendix C — Figure index

The 13 figures in this report (all self-authored schematic/framework figures; any capacity numbers tagged "model" are estimates): fig_weekly_delta (this week's delta), fig_global_map (global map), fig_kr_map (Korea corridor), fig_fab_timeline (project Gantt), fig_wpm_bridge (capacity bridge), fig_capex_flow (transmission framework), fig_five_lines (five pull lines), fig_equipment_matrix (segment positioning), fig_moat_tiers (three-tier pyramid), fig_frontend_loop (front-end loop), fig_nand_structure (3D NAND structure), fig_hbm_stack (HBM cross-section), fig_hbm_backend_flow (HBM backend line).

v1.0, 2026-07-03. Data conflicts per Appendix B; two hard conflicts — P5 capacity (6k vs 60k WPM) and SMEE lithography level (KrF vs DUV) — remain flagged unverified. Figures marked "model/est." are modeled, not official disclosure. For study, not investment advice.